Protel 99se absolute origin how to#
Protel 99se absolute origin manual#
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Protel 99se absolute origin trial#

It raises the specific question of how PCB software handles split planes. I have now finished this board but could not avoid some weird issues. I would hope the $10k-20k ones (which Protel PCB morphed into) are absolutely perfect and don't need these silly stunts to define split planes I don't know if the $1000 programs people use nowadays are any better. One other thing which is generally necessary for the program to correctly allocate nets to objects is to unload the netlist, reload it, and Autoroute All to remove the ratsnest. I suspect they are relative to some undocumented origin point. Magically most of the clearance errors have disappeared, but the aforementioned coordinates still don't make sense.

Protel 99se absolute origin manual#

I looked up the manual for Protel 99SE (which I also have but have not used it so far) and it does the same thing, except that they have renamed the feature as a Split Plane, and documented it somewhat better. When this feature is used to produce a filled polygon, the grid value controls the pitch at which the tracks are placed, so typically you might use 0.030 track and 0.025 grid to make sure the fill is full. That grid parameter is certainly not a grid for the polygon placement. I have not spent more time on it since it is obvious that there will be a connection on the real PCB, but it might be that this mysterious value controls some sort of grid on which the connectivity is checked and if the channel left is narrower than the grid then no connectivity will be found. This seems to be an undocumented feature. However I am still finding that the long and narrow vertical portion (on the RHS of the PCB) of the plane is not making a connection. The polygon plane must be placed so it exactly encloses the area which is to be isolated, meaning that the end point must be exactly over the start point (not enough for the tracks to touch). 8 ) it differs from the reference manual wording in that this is called a Polygon Plane. The only thing it recognises is a polygon. This stuff is actually in the reference manual. I remember something from a decade ago: Protel PCB doesn't recognise normal tracks (placed into a plane) as breaking the plane. Clearance Error Track (1138mil,2581mil 1268mil,2581mil) Top Layer +DCIN Pad (1138mil,2583.047mil) Multi-Layer No Net Clearance Error Track (3293mil,2681mil 3293mil,2741mil) Top Layer GND_2 Pad (3293mil,2743mil) Top Layer GND_1 Clearance Error Track (3388mil,2186mil 3388mil,2281mil) Top Layer -20V_2 Pad (3388mil,2286mil) Top Layer No Net Many thanks for any tips. I also wonder if anyone knows what the coordinates in the DRC error listing mean? They are not within the PCB area. However listing broken subnets when actually there is some clearance error or a short, has always been a feature of Protel PCB. The DRC errors are listed as broken subnets, but clearly they are physically connected within each piece of the plane. Usually, by clicking on some random track, the DRC error goes away, but I have spent a few days on this and can't solve it. There are cases where one has to just give up and accept some DRC errors but I don't like doing it. I wondered if one is supposed to use a Polygon Plane? I tried that and it doesn't seem to make any difference. The way to generate split planes is to place a track on the plane layer.

I have carefully checked that the tracks placed on the Plane 1 layer have no breaks in them, since that would be an obvious cause. But Protel is in some cases joining them up - as if the planes were joined. I have this PCB with a split ground plane (Internal Plane 1): Placing pads in each these four areas, with all the pads having a 'relief to Plane 1' should not produce a conflict.

Protel 99se absolute origin how to#

But now I have a weird problem and wonder if somebody of sufficient age might remember how to deal with it.

Protel 99se absolute origin trial#

I am also more than familiar with its cryptic and mostly useless DRC errors, which in most cases are solved by trial and error only the. It works great and I have done many many designs with it.

I am running this old prog under a winXP VM.